Gossamer – Joint European research project for the development of flash memory devices

In recent years, the demand on memory devices increased continuously. Especially for the flash memory, used e. g. in digital cameras or mobile phones to store multimedia data, the market is growing rapidly. The topic of the "Gossamer" project aims at the development and implementation of next generation Flash memory devices on 300 mm wafers. Considered solutions focus on solid state disc applications, which are discussed as an alternative to the magnetic storage media. Therefore a technology has to be developed for a sub-30 nm target cell size where conventional flash memory concepts reach their physical limit. As a final outcome for this technology, the readiness for start of production will be demonstrated. Together with Fraunhofer CNT, Qimonda accompanies this project as an industrial partner. Besides other European companies, research institutes and universities of the semiconductor sector, e. g. Numonyx (Italy), IMEC (Belgium), ASM-I etc., are as well involved in the Gossamer project, which is funded by the European Union.
The main tasks of Fraunhofer CNT within this project are:
• materials research (dielectric and electrode materials)
• integration of new materials in the process flow
• electrical characterization of dielectric layers and memory cells
• investigation of methods to increase the storage density

Within a flash memory a lot of single cells are linked together to a so-called NAND array where 32 cells along the bitline (BL) form a string. Each crosspoint of wordline (WL) and BL represents a single cell transistor where information is stored as electronic charge in an additional trapping layer. In contrast to volatile memory devices (e. g. DRAM), the information is conserved here even if the voltage supply is removed.
The TANOS memory cell is formed as a stack of different materials. The name „TANOS" derives from the top-down sequence of layers: the tantalum nitride gate electrode of the cell transistor, the isolating aluminia layer, the non-conducting silicon nitride layer and below this stack a thin silicon oxide layer which separates the stored charge from the silicon of the transistor channel. This cell concept belongs to the so-called charge trap memory devices, as the charge is stored at traps in the silicon nitride layer. During the programming procedure, electrons are transferred to the silicon nitride layer. The stored charges cause a threshold voltage shift of the transistor which enables to distinguish clearly between the programmed and erased state of the device cell. These states represent the stored information that can be translated into digital codes (bits).